    [Patent Document 1] JP11-176177
A NAND-type flash memory is formed of a memory array with a plurality of NAND series configured as matrix. The NAND series are formed of a plurality of memory cells coupled in series and selection transistors coupled to two ends of the NAND series, wherein one end is coupled with a bit line through the selection transistor, and another end is coupled to a source line through the selection transistor. Reading and programming (writing in) of a data is performed by the bit line coupled with the NAND series.
FIG. 1 is a schematic diagram illustrating a bit line selection circuit of a conventional flash memory. An even number bit line BLe and an odd number bit line BLo in FIG. 1 are a pair of bit lines. A bit line selection circuit 300 has a first selection unit 310 including a transistor BLC that couples the even number bit line BLe or the odd number bit line BLo with a sensing amplifier 330 (S/A), transistors BIASe and BIASo selectively applying a bias voltage VPRE to the even number bit line BLe and odd number bit line BLo, and a second selection unit 320 including transistors BLSe and BLSo that couple the even number bit line BLe and odd number bit line BLo with the first selection unit 310.
To pre-charge a write-in disable bit line to a prescribed bias voltage when performing a programming operation or pre-charge all of the bit lines to an erasing voltage to apply the erasing voltage to a cell well when performing an erasing operation, the bias voltage transistors BIASe and BIASo and the selection transistors BLSe and BLSo of the second selection unit 320 are formed of high voltage transistors having a thick gate oxidation film and a long gate.
When a page is read from the flash memory, a page formed by the even number bit line (hereinafter “even number page” for simplicity) or a page formed by the odd number bit line (hereinafter “odd number page” for simplicity) are alternately read for reading. When the even number page is selected, the even number page is coupled to the sensing amplifier to be read. Meanwhile, the unselected odd number page is separated by the sensing amplifier and is supplied with a shielding potential equivalent to a ground level (0V), thereby reducing noise through capacitance coupling between the adjacent bit lines. This is the so-called bit-line shielding (Patent Document 1).
The sensing amplifier includes a sensing circuit sensing a voltage or current read from the bit line, a latch circuit preserving data or writing in data, etc. The sensing circuit/latch circuit of the sensing amplifier are selectively shared by an even number bit line and an odd number bit line. Therefore, the sensing amplifier has a sensing circuit/latch circuit for one page, whereas a word line on the memory array is coupled to memory cells for two pages (even and odd number pages). A sensing circuit/latch circuit allocates two bit lines (even number bit line and odd number bit line). Given that the even and odd number pages are alternately read, although the word line has a two-page structure, two pages are not simultaneously read. Therefore, it is inevitable that a high-speed effect cannot be arrived at. Programming is also performed with the even number page or odd number page as a unit.
One further development is that a pair of sensing amplifiers is disposed at two sides of a memory array, wherein one of the sensing amplifiers is coupled to the even number bit line, and the other of the sensing amplifier is coupled to the odd number bit line. In addition, a sensing circuit/latch circuit is distributed to a bit line, such that the flash memory is allowed to read or program two pages, even number page and odd number page, at the same time.
However, in this kind of flash memory, since the even number bit line end and the odd number bit line end are driven by respective of the sensing amplifiers, a capacitance for a bit line increases as a number of word lines increases due to higher density, and the demand to the driving ability of the sensing amplifier consequently increases. To improve the driving ability of the sensing amplifier, a higher voltage and a transistor in a relatively larger size become necessary. Therefore, the sensing amplifier disposed at two sides of the memory cells become less preferable in terms of spatial utilization.
Moreover, in the flash memory in which reading and programming is performed by alternately performing the operation to the even number page or odd number page, the technology of bit line shielding may be replaced to improve a data-reading speed from the memory array. Since there are fewer sensing amplifiers, it has the advantage of a higher integration of memory.